1. Field of the Invention
The present invention relates to a static random access memory (SRAM) having thin film transistors (TFT's) as loads.
2. Description of the Related Art
A typical SRAM includes a plurality of word lines, a plurality of pairs of bit lines, and static memory cells connected to one of the word lines and one pair of the bit lines. Also, one static memory cell is comprised of a complementary flip-flop formed by two load P-channel metal oxide semiconductor (MOS, broadly, MIS) transistors and two driving N-channel MOS transistors, and transfer gates interposed between the flip-flop and the bit lines.
Recently, TFT's have been used as the above-mentioned load P-channel MOS transistors, to thereby improve the integration and reduce the power dissipation (see: JP-A-HEI2-14565).
In the above-mentioned SRAM using the TFT's as the memory cell loads, however, the threshold voltage of the TFT's is affected by electric fields of the bit lines, and as a result, a driving power supply voltage limit value and a data hold voltage for the memory cells become high. This will be explained later in detail.